1. Field of the Invention
This invention relates to peak detector circuits and, more particularly, to a peak detector which can detect high and low level voltages near the upper power supply (e.g., V.sub.DD) or the lower power supply (e.g., ground).
2. Description of the Related Art
In almost all digital systems, a distinction is made between a logic high level and a logic low level. In metal oxide semiconductor (MOS) technologies, a high logic level is substantially near an upper power supply while the logic low level is substantially near a lower power supply. However, in emitter coupled logic (ECL) the high and low logic levels are within a range fairly close to one another generally near the upper power supply.
To discern logic high and low levels, it may be advantageous to implement a peak detector. The peak detector determines if an input voltage applied to the detector is either at a high voltage level or a low voltage level. For ECL voltage levels, the peak detector must be quite sensitive to slight variations in the input voltage or voltages and must discern those variations at or near either the upper or the lower power supplies. Peak detectors may also be used in analog circuitry. It is oftentimes desirable to determine the global minimum of two or more sinusoidally varying input voltages and provide that minimum as an output to other circuitry. Accordingly, the peak detector operates to detect information within either an analog or a digital input signal.
FIG. 1 illustrates one example of a negative peak detector 10 configured to receive a pair of input signals, labeled as input1 and input2. Peak detector 10 is shown for illustrative purposes as a negative peak detector. Peak detector 10 compares the two input signals, and the smallest magnitude input signal is tracked and thereafter passed to the output signal. If either input1 or input2 decreases, that decrease is recorded as a decrease in the output, as shown in the input and output graphs provided. However, at input voltage levels near the upper power supply, the output cannot properly track for reasons better illustrated in FIG. 2.
FIG. 2 illustrates one example of how a conventional negative peak detector might be implemented. A typical negative peak detector 10 is shown having at least two differential p-channel pairs of transistors 14 and 16. Transistor pairs 14 and 16 are arranged in a folded layout, with an output node Vout coupled in feedback with the inputs and outputs of transistors 14b and 16a of the transistor pairs 14 and 16. A pair of diodes 18 and 20, coupled within the feedback loop, capture the lowest (or negative) peak voltage applied to the input signal Vin1 or Vin2.
As illustrated in FIG. 2, when the input voltages Vin1 and Vin2 are higher than the output voltage Vout, diodes 18 and 20 are reverse biased and remain in their "off" state. The output voltage therefore remains approximately constant or, as will be described herein, will slowly leak upward to the upper power supply (e.g., V.sub.DD). The differential pairs of transistors 14 and 16, however, have a disadvantage in that they may not properly function if the input voltages approach the upper power supply. Transistors 14a and 16b, and their associated tail currents (i.e., current sources), operate most effectively when the maximum input voltages applied to their gate conductors are limited to the power supply voltage minus (i) the source-to-drain saturation voltage of the current sources 22 and 24, and minus (ii) the source-to-gate threshold voltages of the transistors 14a and 16b. Current sources 22 and 24 can be effectuated by a single transistor connected to receive a constant DC bias voltage, or a cascoded pair of transistors each of which is coupled to receive a DC bias voltage. In either instance, a voltage difference exists across current sources 22 and 24. If Vin1 and Vin2 exceed this maximum, current sources 22 and 24 may not fully conduct into the saturation region. Using typical values of between 200 to 300 mV for the source-to-drain saturation voltage and 800 to 1200 mV for the source-to-gate operating voltage results in a maximum input voltage of V.sub.DD -1.0 volt to V.sub.DD -1.8 volts. In the latter instance, the current source is produced by a cascoded pair of transistors, each having approximately 300 mV source-to-drain drop.
If the high and low voltage ECL levels are in a range which exceed the maximum input voltage, then those levels cannot be discerned. This would possibly be the case if the low voltage level (i.e., Vol) is greater than V.sub.DD -1.8 volts in the example provided herein above. It would therefore be desirable to derive a negative peak detector which can track input voltages which are at or substantially near the upper power supply in instances when the input voltages to be detected are in a range close to that supply. Conversely, it may also be desirable to derive a positive peak detector which can track input voltages at or substantially near the lower power supply. A positive peak detector can advantageously be used to determine high and low voltage levels if the range of those levels are chosen near ground.